Avalon ST custom IP component

Ready latency only compensates for the pipelining within your own component and doesn't take the rest of the system into consideration. So if you pipelined the data, valid, sop, eop signals you would declare that to have a ready latency of 1 because valid data gets asserted one cycle after the source ready signal asserts. Section 5.9 shows some examples of what I mean by ready latency: https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/manual/mnl_avalon_spec.pdf

If you don't put any pipeline stages into your core then by definition it must set the ready latency to 0. If the delay through your core is too high then you should see a setup timing violation from the path through your IP core.

Have you simulated your design, typically for functional timing issues simulations will make finding these issues much easier. Alternatively you could signaltap the source and sink ports of your core to see how it behaves in silicon, but you need to make sure those paths meet timing otherwise you will not be able to trust the samples collected.