Honored Contributor
Honored ContributorThank you for explaining that to me. Since I'm not using any pipelining just for now I assume that my ready latency is 0. I tried to signaltap my design but since I'm not meeting the timings just as you set I just get zeros and none of the sources and sinks have any valuable data (is it normal for signaltap to set all of the other sources and signals even before my component to 0? Because I also tried to look at the signals in the frame reader but they are also just 0).
Anyway, is there a simple way to simulate and testbench the whole QSys system? Because I would like to see how the whole flow of data behaves. I found sth like this, would it do the trick? http://www.alterawiki.com/wiki/simulating_designs_with_lower-level_qsys_systems
