Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Avalon ST custom IP component

Hello, I'm having trouble creating my own component that uses Avalon Streaming Interface in QSys. Based on the VIP demonstartion for DE1-SoC I want to have a connection between the Altera VIP F...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Weird timing I was creating a training and drew a picture of what a streaming dual clock FIFO would look like. Here is the diagram which will give you an idea how to capture or send data to/from a streaming port.

What were you intending with your core, to add a pipeline stage between two streaming cores? If so I think there is a streaming pipeline stage in Qsys already.