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Altera_Forum
Honored Contributor
Honored ContributorAvalon ST custom IP component
Hello, I'm having trouble creating my own component that uses Avalon Streaming Interface in QSys. Based on the VIP demonstartion for DE1-SoC I want to have a connection between the Altera VIP F...
Altera_ForumHonored Contributor
Honored ContributorWeird timing I was creating a training and drew a picture of what a streaming dual clock FIFO would look like. Here is the diagram which will give you an idea how to capture or send data to/from a streaming port.
What were you intending with your core, to add a pipeline stage between two streaming cores? If so I think there is a streaming pipeline stage in Qsys already.
