Avalon ST custom IP component

Thank you for detailed explanation. Right now I created a component with valid, ready, startofpacket, endofpacket bits directly wired and I did the same with the data. So basically all my component does is sending the data through. I attached it to the end of the ST Frame Reader, and put the QSys pipeline after as you suggested. But unfortunately it's not working.

Is it because of the delay in the signals? For example if I changed the readyLatency would it compensate for the fact that the data is streamed through one more component along the way? I know that streaming interface is easy, but I kind of got lost in the way I guess.