Forum Discussion
Honored ContributorAVALON_MM interface of TSE
Hello guys,
In my system ,I want to use TSE without Niosii.I have use it within NiosII and it works very well.I read or wrote the AVALON_MM interface in TSE module to config the inner registers,but it failed when I simulated with my own configuration modle. My question is wether the AVALON_MM can be read or write without NiosII.:confused: Thanks.31 Replies
Altera_ForumSorry for bringing up this old thread but I have the same problem here with a tse_mac that was originally used with a NIOS and shall now be used without one. I also have the problem, that the waitrequest signal is never deasserted. I simulated for > 18 ms so I do not think it is an initialization delay or something like that.
Regards flint- Altera_Forum
Do you provide all the clocks (including the Avalon streams and the MII interface)?
Did you check the polarity of the reset signal? Do you send a reset pulse at the beginning of the simulation? - Altera_Forum
Hello,
I think I connected everything I should: Clocks: clk ff_rx_clk ff_tx_clk rx_clk tx_clk are all connected to the same 125 MHz clock. I provide a reset on simulation start for 100 ns, after reset goes low the mdc clock output starts so I think this is correct. Regards flint - Altera_Forum
What operation do you do, when you have the wait request signal asserted? Is it the first one?
- Altera_Forum
The waitrequest signal is high right from the start. I do no operation. I tried to read out the version register and write and read the scratch register but this does not work (as one might expect with the waitrequest signal high).
Regards flint - Altera_Forum
Did you try the testbench generated by the megawizard, to see if there is any difference with your test?
- Altera_Forum
Hi,
sorry for not posting in the previous week, I was on vacations. Indead your tip to compare against the provided testbench brought me to the solution: I had a misconception over the semantics of the waitrequest signal, it is high per default, then you start a transaction (read or write) and on the end of this transaction the signal goes low for one clock cycle to signal that you can start the next transaction. Now I can write and read the scratch register with arbitrary values so I assume register access works. Maybe my fault because I did not read the Avalon-MM spec, only the Avalon-ST. Thanks for your help, flint - Altera_Forum
Hi,
I am also having trouble with waitrequest high... I am just trying to write the scratch register (address 8'h01) with 32'haaaaaaaa but not successful as waitrequest signal is high throughout simulation :(.. I am providing 50 MHz clk for Avalon-MM interface and 125MHz clk for ff_tx_clk, ff_rx_clk, tx_clk, rx_clk. Also when Analysis and Elaborating the project using Quartus II 10.1, got the warning "Warning (10236): Verilog HDL Implicit Net warning at altera_tse_rx_stat_extract.v(112): created implicit net for "reset_rx_clk"". How to resolve this warning as it is in encrypted file.. Regards, Sawaak - Altera_Forum
Did you reset the TSE first? Did you check the polarity of the reset signal?
- Altera_Forum--- Quote Start --- Did you reset the TSE first? Did you check the polarity of the reset signal? --- Quote End --- Hi, Yes, I have applied the reset and the polarity is high. regards, sawaak
