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Altera_Forum
Honored Contributor
Honored ContributorAVALON_MM interface of TSE
Hello guys, In my system ,I want to use TSE without Niosii.I have use it within NiosII and it works very well.I read or wrote the AVALON_MM interface in TSE module to config the inner registers,bu...
Altera_ForumHonored Contributor
Honored ContributorHi,
I am also having trouble with waitrequest high... I am just trying to write the scratch register (address 8'h01) with 32'haaaaaaaa but not successful as waitrequest signal is high throughout simulation :(.. I am providing 50 MHz clk for Avalon-MM interface and 125MHz clk for ff_tx_clk, ff_rx_clk, tx_clk, rx_clk. Also when Analysis and Elaborating the project using Quartus II 10.1, got the warning "Warning (10236): Verilog HDL Implicit Net warning at altera_tse_rx_stat_extract.v(112): created implicit net for "reset_rx_clk"". How to resolve this warning as it is in encrypted file.. Regards, Sawaak
