Hi,
sorry for not posting in the previous week, I was on vacations.
Indead your tip to compare against the provided testbench brought me to the solution: I had a misconception over the semantics of the waitrequest signal, it is high per default, then you start a transaction (read or write) and on the end of this transaction the signal goes low for one clock cycle to signal that you can start the next transaction. Now I can write and read the scratch register with arbitrary values so I assume register access works.
Maybe my fault because I did not read the Avalon-MM spec, only the Avalon-ST.
Thanks for your help,
flint