Avalon Interconnect Dynamic Bus Sizing and Bursts

I forgot to mention I did not pull in the ram module in the simulation, you will have to add it to the *.do file before run -a. Here is the screenshot, the current test is the readata is 16bits while the write data at the master is 32bits.

Would you please mark the important regions in your screenshot? I can not see any signal regarding the burstcount. I can only see that burstcount is in an invalid state 'X'.

I checked your qsys design => the onchip ram has 32bit avalon mm bus => so there wont be any translation.

Is the onchip_ram even bursting capable? I don't think so. i cant see any bustcount signals.

Yes, it is supported. you can't see the burst count because the screenshot does not show the whole waveforms. You can try run the design attached to see it.

Thanks

in your design i could not see any burst signals to the onchip ram in the qsys schematic view , so i think there will be a bursting adapter in your interconnect.

=> would you show me a screenshot of your qsys schematic

Yes, it should be on the bursting adapter. You can check where does the adapter being inserted in the qsys.

in qsys -> press system -> show system with interconnect -> memory mapped interconnect

You can also explore what it have under system with interconnect.

any update?