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sadad's avatar
sadad
Icon for New Contributor rankNew Contributor
6 years ago

Avalon Interconnect Dynamic Bus Sizing and Bursts

Hello! My Avalon-MM master has 32bit data width and is bursting capable. Now i connect an Avalon-MM slave with 8bit data width which is also bursting capable. Will a 32bit read or write access to ...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago

I forgot to mention I did not pull in the ram module in the simulation, you will have to add it to the *.do file before run -a. Here is the screenshot, the current test is the readata is 16bits while the write data at the master is 32bits.