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sadad's avatar
sadad
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7 years ago

Avalon Interconnect Dynamic Bus Sizing and Bursts

Hello! My Avalon-MM master has 32bit data width and is bursting capable. Now i connect an Avalon-MM slave with 8bit data width which is also bursting capable. Will a 32bit read or write access to ...
sadad's avatar
sadad
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6 years ago

Would you please mark the important regions in your screenshot? I can not see any signal regarding the burstcount. I can only see that burstcount is in an invalid state 'X'.

I checked your qsys design => the onchip ram has 32bit avalon mm bus => so there wont be any translation.