agilex 7 Platform Designer PIO addr width

I am aware that the example project uses the "PIO Design Example for PCI Express Gen4" module, which defaults to a 16 KB address range mapping. Therefore, I have switched to using the PCIe PIO module.

I have identified the root cause of the issue and verified that the modification is effective. In the code generated by PIO, certain default macro parameters restrict the accessible memory region to only 1 MB under default configuration. I believe this is an issue with the IP core, as it may mislead or confuse users unfamiliar with this detail (the PIO module only allows configuration of the data access width; however, with the default address range set to 64-bit, the effective accessible address range is limited to merely 1 MB).  

Additionally, is there any official documentation available specifically for this PIO module?

This mask prevents me from accessing a larger address range.

Thank you very much for your suggestions. Regarding the DMA-related content, I haven't implemented it yet (including the PCIe AVST DMA example project). If I want to use DMA to access the on-chip RAM, which example project would be more suitable: PCIe AVST DMA or PCIe Multichannel DMA?

After you expand the BAR0 size, you'll need to expand some related modules inside PCIe PIO as well if you really need 2M size. if you'd like to check, a performance design like DMA doesn't always require a large BAR0. The way to use on-chip ram is important.

Since the PIO module does the AVST to AVMM transformation, here are some places I think you can try. Below filenames could be different from yours.

After the completion of Synthesis, you can find below module in ip/pcie_ed/pcie_ed_pio0/synth/pcie_ed_pio.v.

You may increase the PIPELINE_EN to a larger number.

This file ip/pcie_ed/intel_pcie_pio_g4_2431/synth/intel_pcie_bam_sch_intf_pipeline.sv does HIP to AVMM conversion. 

Right there, you can find a 16KB FIFO here. I think you need to expand both read and write FIFOs for a larger amount of data.

Regards,

Rong

Hi,

AVMM is no longer used in PCIe example designs. If you still want to use PCIe+AVMM, you can upgrade your original design to a newer Quartus. 

If you want to try PCIe+AVST and have problem in using the BAR0, please let me know your Quartus version.

Regards,

Rong