New Contributor
New ContributorI am aware that the example project uses the "PIO Design Example for PCI Express Gen4" module, which defaults to a 16 KB address range mapping. Therefore, I have switched to using the PCIe PIO module.
I have identified the root cause of the issue and verified that the modification is effective. In the code generated by PIO, certain default macro parameters restrict the accessible memory region to only 1 MB under default configuration. I believe this is an issue with the IP core, as it may mislead or confuse users unfamiliar with this detail (the PIO module only allows configuration of the data access width; however, with the default address range set to 64-bit, the effective accessible address range is limited to merely 1 MB).
Additionally, is there any official documentation available specifically for this PIO module?
This mask prevents me from accessing a larger address range.
Thank you very much for your suggestions. Regarding the DMA-related content, I haven't implemented it yet (including the PCIe AVST DMA example project). If I want to use DMA to access the on-chip RAM, which example project would be more suitable: PCIe AVST DMA or PCIe Multichannel DMA?
