Forum Discussion

xiaohao's avatar
xiaohao
Icon for New Contributor rankNew Contributor
16 days ago

agilex 7 Platform Designer PIO addr width

I am using the PIO example design of the P-Tile AVST PCIe IP on Intel Agilex 7. The original design maps a 16KB RAM to BAR0. Since my design requires a larger address space, I modified the PCIe IP's ...
Pcie
RongY_altera's avatar
RongY_altera
Icon for Contributor rankContributor
15 days ago

Hi,

 

AVMM is no longer used in PCIe example designs. If you still want to use PCIe+AVMM, you can upgrade your original design to a newer Quartus. 

 

If you want to try PCIe+AVST and have problem in using the BAR0, please let me know your Quartus version.

 

Regards,

Rong

 

xiaohao's avatar
xiaohao
Icon for New Contributor rankNew Contributor
15 days ago

I am using Quartus 24.1. I believe I may not have expressed myself clearly earlier: I am not using a PCIe IP with an AVMM interface; rather, I am accessing the RAM directly via PIO. The core of my issue lies in the intermediate PIO conversion module, which has a constrained address range. For example, when performing a read or write operation to address 0x1FFFF0, the address is altered to 0x0FFFF0 after passing through the PIO module.