New Contributor
ContributorHi,
AVMM is no longer used in PCIe example designs. If you still want to use PCIe+AVMM, you can upgrade your original design to a newer Quartus.
If you want to try PCIe+AVST and have problem in using the BAR0, please let me know your Quartus version.
Regards,
Rong
New ContributorI am using Quartus 24.1. I believe I may not have expressed myself clearly earlier: I am not using a PCIe IP with an AVMM interface; rather, I am accessing the RAM directly via PIO. The core of my issue lies in the intermediate PIO conversion module, which has a constrained address range. For example, when performing a read or write operation to address 0x1FFFF0, the address is altered to 0x0FFFF0 after passing through the PIO module.
ContributorThanks. Now I understand.
Can you share me the output of lspci?
Regards,
Rong
New Contributorsudo lspci -s 0000:01:00.0 -v
01:00.0 Unassigned class [ff00]: Altera Corporation Device 0001 (rev 11)
Flags: fast devsel, IOMMU group 12
Memory at fa00000000 (64-bit, prefetchable) [size=2M]
Capabilities: [40] Power Management version 3
Capabilities: [70] Express Endpoint, MSI 00
Capabilities: [100] Advanced Error Reporting
Capabilities: [148] Virtual Channel
Capabilities: [178] Alternative Routing-ID Interpretation (ARI)
Capabilities: [188] Secondary PCI Express
Capabilities: [1b8] Physical Layer 16.0 GT/s <?>
Capabilities: [1e8] Lane Margining at the Receiver <?>
Capabilities: [470] Data Link Feature <?>
Capabilities: [d00] Vendor Specific Information: ID=1172 Rev=0 Len=05c <?>
