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RamaMohan's avatar
RamaMohan
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

A10 PCIe SRIOV IP not sending completion to Root Port

We are trying to run a simulation with A10 PCIe+SRIOV IP, where Root Port is trying to access a registers behind BAR0 of the IP. There is a write followed by 3 reads from Root Port and the completions for the 3 reads are sent to PF0 of the IP. The IP successfully transmitted 2 Read Completions back to Root Port, but the 3rd completion is stuck in the IP. The Root Port have infinite completion credits, which can be seen on tx_cred* status signals and the IP debug status signals do not indicate any error on the Tx Packets. The simulation fails with completion timeout on the 3rd Read.

Attached is TLP transactions log dump by the IP and completions sent to IP on the AVST-Tx Interface.

We don't understand what is the issue in the IP here.

Thanks,

RamaMohan

11 Replies

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    ​Hi Sir,

    Just try to understand if there is any read address dependency, if the third read is the same address with the previous one (successfully read), do you observe the same problem?

    Regards -SK

  • RamaMohan's avatar
    RamaMohan
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago
    Hi SK, I don’t see any read address dependencies. But I shall try with same address and let you know. Thanks, Ramamohan
  • RamaMohan's avatar
    RamaMohan
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago

    Hi SK,

    If the second address is repeated for third read transaction as well, I'm not seeing any issue. Please clarify how address is impacting the completion to be sent by the PCIe IP.

    The successful completion TLP is

    31:0 - 32'h4A000001

    63:32 - 32'h01000004

    95:64 - 32'h0000001C

    127:96 - 32'h00000000

    159:128 - 32'h00000000

    191:160 - 32'h00000000

    223:192 - 32'h00000000

    255:224 - 32'h00000000

    Where as unsuccessful completion TLP is as below:

    31:0 - 32'h4A000001

    63:32 - 32'h01000004

    95:64 - 32'h00000000

    127:96 - 32'h00000000

    159:128 - 32'h00000000

    191:160 - 32'h00000000

    223:192 - 32'h00000000

    255:224 - 32'h00000000

    The only difference is the lower_address which is 0x1C for successful reads and 0x00 for blocked read.

    Thanks,

    RamaMohan

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    ​Hi RamaMohan,

    Can you also share with us the Read Request TLP to compare the difference for two cases? Is this only address 0 having this problem?

    Regards -SK

  • RamaMohan's avatar
    RamaMohan
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago
    Hi SK, Here’s the list of Read req/rsp we tried, from IP logfile altpcie_monitor_a10_dlhip_tlp_file _log.log. Only the completion of last request(marked Bold) is not sent out by the IP. So far we are observing this behavior only with address 0. | 332 RX | MWr | 0004 | 60000001_0000000F_00000020_0000E014 | | 332 RX | MRd (00) | 0004 | 20000001_0000000F_00000020_0000E014 | | 332 TX | CplD (00) | 0004 | 4A000001_01000004_00000014 | | 333 RX | MRd (00) | 0004 | 20000001_0000000F_00000020_0000E01C | | 333 TX | CplD (00) | 0004 | 4A000001_01000004_0000001C | | 334 RX | MRd (00) | 0004 | 20000001_0000000F_00000020_0000E01C | | 334 TX | CplD (00) | 0004 | 4A000001_01000004_0000001C | | 335 RX | MRd (00) | 0004 | 20000001_0000000F_00000020_0000E01C | | 335 TX | CplD (00) | 0004 | 4A000001_01000004_0000001C | | 336 RX | MRd (00) | 0004 | 20000001_0000000F_00000020_0000E01C | | 336 TX | CplD (00) | 0004 | 4A000001_01000004_0000001C | *| 337 RX | MRd (00) | 0004 | 20000001_0000000F_00000020_0000E000 |* Thanks, RamaMohan
  • RamaMohan's avatar
    RamaMohan
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago

    Hi SK,

    I tried varying addresses and the issue is occurring with addresses other than 0 as well. Please find the attached snapshot that has occurred with address:8.

    Thanks,

    RamaMohan

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    ​Hi Ramamohan,

    Could you please share with us your simulation project, and also provide the exact steps to replicate the problem?

    Regards -SK

  • RamaMohan's avatar
    RamaMohan
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago
    Hi SK, I may not be able to share the project with you as this have third party IPs and confidential code. I can share the PCIe IP configuration parameters (.ip) that we are using. Thanks, RamaMohan
  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    ​Hi RamaMohan,

    It will be great if there is an environment to replicate the problem, and further look into it. But as for now, I don't see there is an example for Arria 10 SRIOV available for testing.

    Regards -SK

  • RamaMohan's avatar
    RamaMohan
    Icon for Occasional Contributor rankOccasional Contributor
    7 years ago

    Hi SK,

    I see your point that you are not able to replicate the issue at your end. In general what will be your approach to replicate these kind of issues at your end.

    Since your SRIOV PCIe IP model is encrypted we are also not able to get insight on the root cause. What we observe is that the interface signals are being driven as per the requirements in the A10 PCIe SRIOV user-guide. The same is shared with you via snapshots.

    When you ask for simulation project what all do you expect to be shared. If you let me know this information in detail I may work to see what can be done to share the required information with you.

    Also, let me know if it is possible for you to provided the un-encrypted model for our simulation.

    Thanks,

    RamaMohan