Forum Discussion
RamaMohan
Occasional Contributor
Occasional ContributorA10 PCIe SRIOV IP not sending completion to Root Port
We are trying to run a simulation with A10 PCIe+SRIOV IP, where Root Port is trying to access a registers behind BAR0 of the IP. There is a write followed by 3 reads from Root Port and the completion...
SengKok_L_Intel
Regular Contributor
Regular ContributorHi Sir,
Just try to understand if there is any read address dependency, if the third read is the same address with the previous one (successfully read), do you observe the same problem?
Regards -SK
