Forum Discussion
RamaMohan
Occasional Contributor
Occasional ContributorA10 PCIe SRIOV IP not sending completion to Root Port
We are trying to run a simulation with A10 PCIe+SRIOV IP, where Root Port is trying to access a registers behind BAR0 of the IP. There is a write followed by 3 reads from Root Port and the completion...
SengKok_L_Intel
Regular Contributor
Regular ContributorHi RamaMohan,
It will be great if there is an environment to replicate the problem, and further look into it. But as for now, I don't see there is an example for Arria 10 SRIOV available for testing.
Regards -SK
