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RamaMohan
Occasional Contributor
Occasional ContributorA10 PCIe SRIOV IP not sending completion to Root Port
We are trying to run a simulation with A10 PCIe+SRIOV IP, where Root Port is trying to access a registers behind BAR0 of the IP. There is a write followed by 3 reads from Root Port and the completion...
RamaMohanOccasional Contributor
Occasional ContributorHi SK,
I don’t see any read address dependencies. But I shall try with same address and let you know.
Thanks,
Ramamohan
