Forum Discussion
RamaMohan
Occasional Contributor
Occasional ContributorA10 PCIe SRIOV IP not sending completion to Root Port
We are trying to run a simulation with A10 PCIe+SRIOV IP, where Root Port is trying to access a registers behind BAR0 of the IP. There is a write followed by 3 reads from Root Port and the completion...
SengKok_L_Intel
Regular Contributor
Regular ContributorHi RamaMohan,
Can you also share with us the Read Request TLP to compare the difference for two cases? Is this only address 0 having this problem?
Regards -SK
