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RamaMohan's avatar
RamaMohan
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

A10 PCIe SRIOV IP not sending completion to Root Port

We are trying to run a simulation with A10 PCIe+SRIOV IP, where Root Port is trying to access a registers behind BAR0 of the IP. There is a write followed by 3 reads from Root Port and the completion...
RamaMohan's avatar
RamaMohan
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Hi SK,

I see your point that you are not able to replicate the issue at your end. In general what will be your approach to replicate these kind of issues at your end.

Since your SRIOV PCIe IP model is encrypted we are also not able to get insight on the root cause. What we observe is that the interface signals are being driven as per the requirements in the A10 PCIe SRIOV user-guide. The same is shared with you via snapshots.

When you ask for simulation project what all do you expect to be shared. If you let me know this information in detail I may work to see what can be done to share the required information with you.

Also, let me know if it is possible for you to provided the un-encrypted model for our simulation.

Thanks,

RamaMohan