A10 PCIe SRIOV IP not sending completion to Root Port

Hi SK,

If the second address is repeated for third read transaction as well, I'm not seeing any issue. Please clarify how address is impacting the completion to be sent by the PCIe IP.

The successful completion TLP is

31:0 - 32'h4A000001

63:32 - 32'h01000004

95:64 - 32'h0000001C

127:96 - 32'h00000000

159:128 - 32'h00000000

191:160 - 32'h00000000

223:192 - 32'h00000000

255:224 - 32'h00000000

Where as unsuccessful completion TLP is as below:

31:0 - 32'h4A000001

63:32 - 32'h01000004

95:64 - 32'h00000000

127:96 - 32'h00000000

159:128 - 32'h00000000

191:160 - 32'h00000000

223:192 - 32'h00000000

255:224 - 32'h00000000

The only difference is the lower_address which is 0x1C for successful reads and 0x00 for blocked read.

Thanks,

RamaMohan