New ContributorWhy does this code generate extra combinational logic?
The timing analysis indicates the presence of extra levels of combinational logic, but I only have one layer of combinational logic.I don't know where the extra combinational logic is?
The recommended violation resolution methods in the time series analysis report are as follows.
The code for this path is as follows.Among them, clk_6 is a 500MHz clock generated by a PLL.
always@(posedge clk_6 or negedge rst) begin
if(!rst) begin
pps_6<=1'd0;
end
else begin
if(delay_2==4'd5)
begin
pps_6=pps_coarse;end
else begin
pps_6<=1'b0;end
end
end
Below is the timing analysis for the error path.
- Hi,
to answer the question precisely, you can review the post-mapping or post-fitting schematic. It will show you the function of each lcell.
Without seeing the actual logic, I'd guess: The circuit has 5 input bits, 4 delay_2 bits and pps_coarse. Respectively it needs 2 combinational logic cells if it's implemented in 4-input LUTs.
