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student8's avatar
student8
Icon for New Contributor rankNew Contributor
2 years ago
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Why does this code generate extra combinational logic?

The timing analysis indicates the presence of extra levels of combinational logic, but I only have one layer of combinational logic.I don't know where the extra combinational logic is? The recommen...
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  • FvM's avatar
    FvM
    2 years ago
    Hi,
    to answer the question precisely, you can review the post-mapping or post-fitting schematic. It will show you the function of each lcell.

    Without seeing the actual logic, I'd guess: The circuit has 5 input bits, 4 delay_2 bits and pps_coarse. Respectively it needs 2 combinational logic cells if it's implemented in 4-input LUTs.
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

I don't know if this is part of the problem, but when does count_1_l[16] ever get set? Your adder is only adding one to the lower 16 bits:

count_1_l<=count_1_l[15:0]+17'd1;

Is that a typo?

It's not clear why so much logic is between bit 4 and bit 10 but this vector slicing could have something to do with it.

student8's avatar
student8
Icon for New Contributor rankNew Contributor
2 years ago

Thank you for your reply.

in this segment, I calculate the sum of count_1_l[15:0] and 1 each time. The carry bit, count_1_l[16], is assigned as the carry input (cin).

The carry input (cin) is involved in the calculation of count_1_h.

If there is any error in my logic, please point it out.