Forum Discussion
student8
New Contributor
New ContributorWhy does this code generate extra combinational logic?
The timing analysis indicates the presence of extra levels of combinational logic, but I only have one layer of combinational logic.I don't know where the extra combinational logic is? The recommen...
- Hi,
to answer the question precisely, you can review the post-mapping or post-fitting schematic. It will show you the function of each lcell.
Without seeing the actual logic, I'd guess: The circuit has 5 input bits, 4 delay_2 bits and pps_coarse. Respectively it needs 2 combinational logic cells if it's implemented in 4-input LUTs.
FvM
Super Contributor
Super ContributorHi,
to answer the question precisely, you can review the post-mapping or post-fitting schematic. It will show you the function of each lcell.
Without seeing the actual logic, I'd guess: The circuit has 5 input bits, 4 delay_2 bits and pps_coarse. Respectively it needs 2 combinational logic cells if it's implemented in 4-input LUTs.
to answer the question precisely, you can review the post-mapping or post-fitting schematic. It will show you the function of each lcell.
Without seeing the actual logic, I'd guess: The circuit has 5 input bits, 4 delay_2 bits and pps_coarse. Respectively it needs 2 combinational logic cells if it's implemented in 4-input LUTs.
student8Thank you for your reply. This is the post-fitting schematic.
What do you mean by "actual logic" in your reply? chip planner or resource property editor？
The complete code for this section is included in the attachment. I aim to achieve an 8x frequency multiplication of the 500M clock through phase shifting in a (PLL) to achieve precise delay control.
I'm using Cyclone 5CGXFC5C6F23C6, and the underlying architecture should be based on 6-input LUTs.
Thank you again for your response.
