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student8
New Contributor
New ContributorWhy does this code generate extra combinational logic?
The timing analysis indicates the presence of extra levels of combinational logic, but I only have one layer of combinational logic.I don't know where the extra combinational logic is? The recommen...
- Hi,
to answer the question precisely, you can review the post-mapping or post-fitting schematic. It will show you the function of each lcell.
Without seeing the actual logic, I'd guess: The circuit has 5 input bits, 4 delay_2 bits and pps_coarse. Respectively it needs 2 combinational logic cells if it's implemented in 4-input LUTs.
sstrell
Super Contributor
Super ContributorNo. Your carry bit is not going into count_1_l[16] because that bit is not included in your adder. You need to fix your addition:
count_1_l<=count_1_l[16:0]+17'd1;
