Forum Discussion
New ContributorWhy does this code generate extra combinational logic?
- Hi,
to answer the question precisely, you can review the post-mapping or post-fitting schematic. It will show you the function of each lcell.
Without seeing the actual logic, I'd guess: The circuit has 5 input bits, 4 delay_2 bits and pps_coarse. Respectively it needs 2 combinational logic cells if it's implemented in 4-input LUTs.
Super ContributorHi,
the key for explanation is in the logic cell name pps_6~0_RESYN438. Quartus is actually generating extra logic in resynthesis, trying to meet timing, apparently without success.
This would never happen if the basic design achieves timing closure.
I see that the module has multiple input clocks and a variable delay_value input. Without knowing the timing relation of all clocks and delay_value and specified timing constraints, it's impossible to determine if and how the design can meet timing. You have e.g. a pretty long combinational path from delay_value through dividers, unless it's static data flagged as false path, the design can't achieve higher clock rates. Or the output of delay calculation has to be resynced to respective clk_6 domain.
New ContributorThank you very much for your response. Following your advice, I successfully converted delay_value to synchronous logic, eliminating the setup time violation issue from pps_coarse to pps_6.
Unfortunately, my code still has timing problems. As shown in the diagram, there are timing violations between the adders. For example, an illustration is provided below. I'm unsure how to address this issue.
The code for the section, except for the delay_value part, remains unchanged and is the same as the previous attachment.
Once again, thank you for your reply, and I apologize for taking up your time.
