VHDL Strange Behavior

I forgot the Attachment.

I suspect that you're trying to add together 4 inputs in a single clock cycle is causing the problem. Normally, it would be better to pipeline it, doing A+b and C+D in parrallel, then the next clock cycle add the two results and bitshift.

So what's the answer?

As long as the input terms are unregistered and no timing constraints are defined for it, the timing analyzer can't check a required timing. But it reports a required setup and hold time related to clock, that allows to determine the achievable speed even without timing constraints. With Cyclone III slowest speed grade, the worst case setup time is around 6 ns, which is acceptable in my opinion. But you are of course always able to define unsuitable simulation waveforms, thast cause a timing violation.

As Tricky pointed, it is safer to pipeline. It is no good to register output yet add up 4 inputs in combinatorial circuit.

PROCESS(reset_n,clk) 
BEGIN
if reset_n = '0' then
    ...
    ...
    ...
 
elsif clk'EVENT AND clk = '1' THEN 
 
    aux_AB <= (B"00" & A30022)+(B"00" & B30022);
    aux_CD <= (B"00" & C30022)+(B"00" & D30022);
    aux_pij <= aux_AB + aux_CD;
   end if;
END PROCESS;
 
pij <= aux_pij(9 downto 2); -- save 8 registers
 

Yes it might work with modern devices but remember that RTL is based on pipelining to reduce critical paths. A practical project design will not just contain few adders. It is likely to grow till almost of the chip is occupied as managers push in more and more of tasks every morning...

Yes, of course. I was speaking of the particular example with a 4 input adder. As I previously mentioned, the example is incomplete, because the input is unregistered, effectively unrelated to the system clock. This fact was most likely causing confusion in simulating the design. The output is however registered, so it doesn't suggest an endless chain of combinational logic.