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Altera_Forum
Honored Contributor
Honored ContributorVHDL Strange Behavior
Hello, I need to calculate the average between 4 std_logic_vectors: "A, B, C and D". When I simulate my code in modelsim everything seems to be OK:cool:. But, When I test it in t...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I suspect that you're trying to add together 4 inputs in a single clock cycle is causing the problem. --- Quote End --- Depends on... (the FPGA family, the clock frequency). In any case, the timing analyzer would tell.
