Honored Contributor
Honored ContributorYes, of course. I was speaking of the particular example with a 4 input adder. As I previously mentioned, the example is incomplete, because the input is unregistered, effectively unrelated to the system clock. This fact was most likely causing confusion in simulating the design. The output is however registered, so it doesn't suggest an endless chain of combinational logic.
In a real world problem, the input signals would be either registered or have a specified timing relation to the clock. Then you are able to place pipeline stages, where necessary.
