VHDL Strange Behavior

As long as the input terms are unregistered and no timing constraints are defined for it, the timing analyzer can't check a required timing. But it reports a required setup and hold time related to clock, that allows to determine the achievable speed even without timing constraints. With Cyclone III slowest speed grade, the worst case setup time is around 6 ns, which is acceptable in my opinion. But you are of course always able to define unsuitable simulation waveforms, thast cause a timing violation.