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Altera_Forum
Honored Contributor
Honored ContributorVHDL Strange Behavior
Hello, I need to calculate the average between 4 std_logic_vectors: "A, B, C and D". When I simulate my code in modelsim everything seems to be OK:cool:. But, When I test it in t...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- It is no good to register output yet add up 4 inputs in combinatorial circuit. --- Quote End --- It works with 8 bit numbers up to 100 or 200 MHz clock, depending on the device family. Adding two numbers of more common 16 to 32 bit word width results in a higher computational delay. You're free to pipeline everything, of course, but in my opinion, pipelining should be applied where actually required.
