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Altera_Forum
Honored Contributor
Honored ContributorVHDL Strange Behavior
Hello, I need to calculate the average between 4 std_logic_vectors: "A, B, C and D". When I simulate my code in modelsim everything seems to be OK:cool:. But, When I test it in t...
Altera_ForumHonored Contributor
Honored ContributorAs Tricky pointed, it is safer to pipeline. It is no good to register output yet add up 4 inputs in combinatorial circuit.
PROCESS(reset_n,clk)
BEGIN
if reset_n = '0' then
...
...
...
elsif clk'EVENT AND clk = '1' THEN
aux_AB <= (B"00" & A30022)+(B"00" & B30022);
aux_CD <= (B"00" & C30022)+(B"00" & D30022);
aux_pij <= aux_AB + aux_CD;
end if;
END PROCESS;
pij <= aux_pij(9 downto 2); -- save 8 registers
