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Altera_Forum
Honored Contributor
Honored ContributorVHDL Strange Behavior
Hello, I need to calculate the average between 4 std_logic_vectors: "A, B, C and D". When I simulate my code in modelsim everything seems to be OK:cool:. But, When I test it in t...
Altera_ForumHonored Contributor
Honored ContributorYes it might work with modern devices but remember that RTL is based on pipelining to reduce critical paths. A practical project design will not just contain few adders. It is likely to grow till almost of the chip is occupied as managers push in more and more of tasks every morning...
