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Altera_Forum
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15 years ago

VHDL state to entity

Hi,

I have a VHDL design with 8 states. I want to take the state "cur_state" specifically to entity output port.

This is not for debug, but a specific customer requirement.

Please let me know how to do this.

Regards,

freak

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  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Like I said I always verify before I post. My code: 

    
State : out std_logic_vector( 1 downto 0) ;
StateN : out natural ;
...
State <= std_logic_vector( to_unsigned( states_camerastatusLED'pos( smp ) , 2 ) ) ;
StateN <= states_camerastatusLED'pos( smp )  ;

    What error did you get? Did you include the IEEE numeric_std library?

    The natural data type will synthesize to a 31bit-wide vector. You can see this in the 'Tools->RTL Viewer' window. You can constrain the range of the natural to 7 in your case, and you will end up with just 3 pins synthesized. 

    
CurrentStateOut : out natural range 0 to 7 ;
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    obviously the attribute is recognised but what does the error read?

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The code below looks to be working, 

    
CurrentStateOut : out natural ;
CurrentStateOut <= state'pos( curr_state) ;

    The below code is giving out error, 

    
CurrentStateOut <= std_logic_vector(to_unsigned(state'pos(curr_state) ,3));

    Is data dype 'natural' can be synthesized.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi vlsi_freak,

    But Josyb answered you, I simplified his post and FvM endorsed it.

    Regards
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi FvM,

    Can you please provide an example.

    One more thing, Is natural data type synthesizable. ?

    Regards,

    freak
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Using the state'pos attribute is in fact the most reasonable way.

    Alternatively, you can also use the state type in the entity interface, you get a bit vector according to the state machine encoding, one-state-hot state by default. The type has to be defined in a package.

    P.S.: In terms of logic effort, the pos attribute does the same as decoding the states to numbers, as kaz suggested. The internal representation of the state variable will be still one state hot.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Sorry if I sounded like a preacher:)

    I verified the solution in QII 9.1SP2 before committing the post. Attributes are well specified in the VHDL LRM so I don't think that ModelSim will choke on it. (if it does tell me)
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks JosyB,

    In layman terms like myself I believe you mean:

    port declaration:

    CurrentStateOut : out std_logic_vector(2 downto 0);

    then in assignment section:

    CurrentStateOut <= std_logic_vector(to_unsigned(state'pos(curr_state),3));

    Hopefully that will do if tool support doesn't get in the way.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    
CurrentStateOut : out std_logic_vector( ceil(log2( number of states )) - 1 downto 0) ;
---
CurrentStateOut <= std_logic_vector( to_unsigned( state'pos(curr_state) ,  
                               ceil(log2( number of states )) ) ;

    You have to replace the ceil(log2( number of states )) in the port declaration by a fixed number as the size of 'state' is only defined until later in the architecture section.

    If the output is only required for simulation or documentation purposes you could define the output port as a natural: 

    
CurrentStateOut : out natural ;
...
CurrentStateOut <= state'pos( curr_state) ;

    simple, and you don't have to modify the code in case the 'state' definition changes during the design. The only drawback is that the natural is represented as a 31-bit vector, so you may want to restrict the range of the natural.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi,

    Good point. There might be some of those special tool statements to do that(Only FvM knows those secrets) but if it is me I will regenerate a bit of logic:

    case cur_state is

    when idle => out_p <= "000";

    when s1 => out_p <= "001";

    ...etc.

    i.e. you convert it to numerical value onto std_logic_vector.

    Regards