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Altera_Forum's avatar
Altera_Forum
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15 years ago

VHDL state to entity

Hi, I have a VHDL design with 8 states. I want to take the state "cur_state" specifically to entity output port. This is not for debug, but a specific customer requirement. Please let me...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Hi,

Good point. There might be some of those special tool statements to do that(Only FvM knows those secrets) but if it is me I will regenerate a bit of logic:

case cur_state is

when idle => out_p <= "000";

when s1 => out_p <= "001";

...etc.

i.e. you convert it to numerical value onto std_logic_vector.

Regards