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Altera_Forum's avatar
Altera_Forum
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15 years ago

VHDL state to entity

Hi, I have a VHDL design with 8 states. I want to take the state "cur_state" specifically to entity output port. This is not for debug, but a specific customer requirement. Please let me...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks JosyB,

In layman terms like myself I believe you mean:

port declaration:

CurrentStateOut : out std_logic_vector(2 downto 0);

then in assignment section:

CurrentStateOut <= std_logic_vector(to_unsigned(state'pos(curr_state),3));

Hopefully that will do if tool support doesn't get in the way.