VHDL state to entity

Like I said I always verify before I post. My code:

State : out std_logic_vector( 1 downto 0) ;
StateN : out natural ;
...
State <= std_logic_vector( to_unsigned( states_camerastatusLED'pos( smp ) , 2 ) ) ;
StateN <= states_camerastatusLED'pos( smp )  ;

What error did you get? Did you include the IEEE numeric_std library?

The natural data type will synthesize to a 31bit-wide vector. You can see this in the 'Tools->RTL Viewer' window. You can constrain the range of the natural to 7 in your case, and you will end up with just 3 pins synthesized.

CurrentStateOut : out natural range 0 to 7 ;