CurrentStateOut : out std_logic_vector( ceil(log2( number of states )) - 1 downto 0) ;
---
CurrentStateOut <= std_logic_vector( to_unsigned( state'pos(curr_state) ,
ceil(log2( number of states )) ) ;
You have to replace the ceil(log2( number of states )) in the port declaration by a fixed number as the size of 'state' is only defined until later in the architecture section.
If the output is only required for simulation or documentation purposes you could define the output port as a natural:
CurrentStateOut : out natural ;
...
CurrentStateOut <= state'pos( curr_state) ;
simple, and you don't have to modify the code in case the 'state' definition changes during the design. The only drawback is that the natural is represented as a 31-bit vector, so you may want to restrict the range of the natural.
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