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Altera_Forum's avatar
Altera_Forum
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15 years ago

VHDL state to entity

Hi, I have a VHDL design with 8 states. I want to take the state "cur_state" specifically to entity output port. This is not for debug, but a specific customer requirement. Please let me...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The code below looks to be working, 


CurrentStateOut : out natural ;
CurrentStateOut <= state'pos( curr_state) ;

The below code is giving out error, 


CurrentStateOut <= std_logic_vector(to_unsigned(state'pos(curr_state) ,3));

Is data dype 'natural' can be synthesized.