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Altera_Forum
Honored Contributor
Honored ContributorVHDL DE2 board understanding Processes and Signals
So I wrote a program to turn on LEDS if SW, a switch, is '1' and off if '0'.
entity StateLCD is
port(
SW : in std_logic_vector(0 downto 0);
LEDG : out std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(7 downto 0));
end StateLCD;
architecture StateLCD_Behaviour of StateLCD is
SIGNAL LEDState: std_logic_vector(7 downto 0);
begin
process(SW)
begin
if(SW = "1") THEN
LEDState <= "11111111";
else
LEDState <= "00000000";
end if;
LEDG <= LEDState;
end process;
end StateLCD_Behaviour;
8 Replies
Altera_ForumSimple answer: Sensitivity lists are ignored in hardware synthesis.
The bad with the present code is that a RTL simulation behaves different than the hardware.- Altera_Forum--- Quote Start --- So I wrote a program to turn on LEDS if SW, a switch, is '1' and off if '0'.
It works, but shouldn't it only work if I used variables instead of signals? With signals, It seems like the LEDS should be turning off when SW is '1' and turning on at '0' since signals only update at the end of a process. So I would be getting the opposite of the output I want? Where as variables would update immediately. Thanks for any help. --- Quote End --- Variable or signal will do since in both cases the assignment is fixed to same thing that depends only on switch state.entity StateLCD is port( SW : in std_logic_vector(0 downto 0); LEDG : out std_logic_vector(7 downto 0); LEDR : out std_logic_vector(7 downto 0)); end StateLCD; architecture StateLCD_Behaviour of StateLCD is SIGNAL LEDState: std_logic_vector(7 downto 0); begin process(SW) begin if(SW = "1") THEN LEDState <= "11111111"; else LEDState <= "00000000"; end if; LEDG <= LEDState; end process; end StateLCD_Behaviour; - Altera_Forum
your sensitivity list only takes care of "SW", which means your process is only executed when there is any change in SW. signals are updated at the end of process, with your code it means the LEDG is assigned with the existing(previous) value.
anyway, if you want to tie signals to outputs, you don't need to put them inside process - Altera_Forum--- Quote Start --- your sensitivity list only takes care of "SW", which means your process is only executed when there is any change in SW. signals are updated at the end of process, with your code it means the LEDG is assigned with the existing(previous) value. --- Quote End --- As FvM explained, this statement is only true with a simulator. A synthesizer will ignore the sensitivity list, and the best way to simulate what the synthesizer actually does is this code:
I've changed the sensitivity list to contain all the signals that are read by the process. If you simulate this, when you change the switch state the process will be executed a first time, update LEDState, then run a second time and update LEDG. Then you get the same behaviour between the simulation and the synthesized code.process(SW,LEDState) begin if(SW = "1") THEN LEDState <= "11111111"; else LEDState <= "00000000"; end if; LEDG <= LEDState; end process; - Altera_Forum
Ok. i think i might have misunderstood some things. thanks for clearing things up.
- Altera_Forum--- Quote Start --- As FvM explained, this statement is only true with a simulator. A synthesizer will ignore the sensitivity list, and the best way to simulate what the synthesizer actually does is this code --- Quote End --- Why does the synthesizer ignore the sensitivity list though? I don't quite get FvM explanation. Isn't what I'm doing hardware synthesis?
- Altera_Forum--- Quote Start --- Why does the synthesizer ignore the sensitivity list though? I don't quite get FvM explanation. Isn't what I'm doing hardware synthesis? --- Quote End --- It didn't actually explain this point, just stated a fact. Sensitivity lists in asynchronous processes are primarly intended to optimize the operation of a simulator that interprets the HDL code. As a side effect, they work as a kind of software edge detection. Apparently this gives room for a misunderstanding that sensitivity lists can be used for this purpose in hardware design. But the hardware way of evaluating asynchronous HDL code is basically different. The synthesis tools translates it to combinational gate circuits that don't care for state changes, just propagate the combined input data as they are, either if they change every clock cycle or stay for hours. In other words, to answer your question, you should consider how HDL code is mapped to hardware elements.
- Altera_Forum
Sensitivity lists are ignored in hardware synthesis.
