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Why does the synthesizer ignore the sensitivity list though? I don't quite get FvM explanation. Isn't what I'm doing hardware synthesis?
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It didn't actually explain this point, just stated a fact.
Sensitivity lists in asynchronous processes are primarly intended to optimize the operation of a simulator that interprets the HDL code. As a side effect, they work as a kind of software edge detection. Apparently this gives room for a misunderstanding that sensitivity lists can be used for this purpose in hardware design.
But the hardware way of evaluating asynchronous HDL code is basically different. The synthesis tools translates it to combinational gate circuits that don't care for state changes, just propagate the combined input data as they are, either if they change every clock cycle or stay for hours.
In other words, to answer your question, you should consider how HDL code is mapped to hardware elements.
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