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Honored Contributor
Honored ContributorVHDL DE2 board understanding Processes and Signals
So I wrote a program to turn on LEDS if SW, a switch, is '1' and off if '0'. entity StateLCD is
port(
SW : in std_logic_vector(0 downto 0);
LEDG : out std_logic_vector(7 downto 0);
...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Why does the synthesizer ignore the sensitivity list though? I don't quite get FvM explanation. Isn't what I'm doing hardware synthesis? --- Quote End --- It didn't actually explain this point, just stated a fact. Sensitivity lists in asynchronous processes are primarly intended to optimize the operation of a simulator that interprets the HDL code. As a side effect, they work as a kind of software edge detection. Apparently this gives room for a misunderstanding that sensitivity lists can be used for this purpose in hardware design. But the hardware way of evaluating asynchronous HDL code is basically different. The synthesis tools translates it to combinational gate circuits that don't care for state changes, just propagate the combined input data as they are, either if they change every clock cycle or stay for hours. In other words, to answer your question, you should consider how HDL code is mapped to hardware elements.
