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Altera_Forum
Honored Contributor
Honored ContributorVHDL DE2 board understanding Processes and Signals
So I wrote a program to turn on LEDS if SW, a switch, is '1' and off if '0'. entity StateLCD is
port(
SW : in std_logic_vector(0 downto 0);
LEDG : out std_logic_vector(7 downto 0);
...
Altera_ForumHonored Contributor
Honored ContributorSimple answer: Sensitivity lists are ignored in hardware synthesis.
The bad with the present code is that a RTL simulation behaves different than the hardware.
