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Altera_Forum's avatar
Altera_Forum
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13 years ago

VHDL DE2 board understanding Processes and Signals

So I wrote a program to turn on LEDS if SW, a switch, is '1' and off if '0'. entity StateLCD is port( SW : in std_logic_vector(0 downto 0); LEDG : out std_logic_vector(7 downto 0); ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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As FvM explained, this statement is only true with a simulator. A synthesizer will ignore the sensitivity list, and the best way to simulate what the synthesizer actually does is this code

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Why does the synthesizer ignore the sensitivity list though? I don't quite get FvM explanation. Isn't what I'm doing hardware synthesis?