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Honored Contributor
Honored ContributorVHDL DE2 board understanding Processes and Signals
So I wrote a program to turn on LEDS if SW, a switch, is '1' and off if '0'. entity StateLCD is
port(
SW : in std_logic_vector(0 downto 0);
LEDG : out std_logic_vector(7 downto 0);
...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- As FvM explained, this statement is only true with a simulator. A synthesizer will ignore the sensitivity list, and the best way to simulate what the synthesizer actually does is this code --- Quote End --- Why does the synthesizer ignore the sensitivity list though? I don't quite get FvM explanation. Isn't what I'm doing hardware synthesis?
