VGA - horizantal sync pulse generation

hey,

I am trying to generate horizantal sync pulse with FSM.

I write the next verilog code:

 
module horizantal_sync_pluse (
       clock,    //system clock
       reset,   //system reset
       sync_pulse   //horizantal sync pulse
       );
//State machine parameters
parameter Scan_Line=1'b0;
parameter Gen_Sync_Pulse=1'b1;
//----------------------------------
input clock;
input reset;
output sync_pulse;
reg sync_pulse;
reg  state;
reg  counter;
always@(posedge clock, negedge reset)
begin
 if (reset==0) 
 begin 
  state<=Gen_Sync_Pulse;
  sync_pulse<=1'b0;
 end begin
  case (state) 
   Gen_Sync_Pulse:
    if (counter==11'h00BC) begin //188
     counter<=counter+1'b1;
     state<=Gen_Sync_Pulse;
     sync_pulse<=1'b0;
    end else
    begin
     state<=Scan_Line;
    end
   Scan_Line:
    if (counter==11'h639) begin
     sync_pulse<=1'b1;
     counter<=counter+1'b1;
     state<=Scan_Line;
    end else
    begin
     state<=Gen_Sync_Pulse;
     counter<=0;
    end
    default:
     state<=Gen_Sync_Pulse;
     
   endcase
end
end
endmodule

after compilation I get Warning: Latch counter[0] has unsafe behavior

Warning: Ports D and ENA on the latch are fed by the same signal sync_pulse~5

This warning is on each bit of the counter.

why is it? how can I avoid it?

Thanks