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Altera_Forum
Honored Contributor
Honored ContributorVGA - horizantal sync pulse generation
hey, I am trying to generate horizantal sync pulse with FSM. I write the next verilog code:
module horizantal_sync_pluse (
clock, //system clock
reset, //system ...
Altera_ForumHonored Contributor
Honored ContributorWell you can just not declare the unwanted parameters and use their assigned values directly in your code to replace their names.
Parameter is for helping code readability/updating only. At compile time they are replaced by its value.
