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Altera_Forum's avatar
Altera_Forum
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14 years ago

VGA - horizantal sync pulse generation

hey, I am trying to generate horizantal sync pulse with FSM. I write the next verilog code: module horizantal_sync_pluse ( clock, //system clock reset, //system ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I haven't done verilog for years but I think you got simple error,

if reset == 0

begin

.....

end

else begin // you should put else here

....