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Altera_Forum
Honored Contributor
Honored ContributorVGA - horizantal sync pulse generation
hey, I am trying to generate horizantal sync pulse with FSM. I write the next verilog code:
module horizantal_sync_pluse (
clock, //system clock
reset, //system ...
Altera_ForumHonored Contributor
Honored ContributorI haven't done verilog for years but I think you got simple error,
if reset == 0 begin ..... end else begin // you should put else here ....
