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Altera_Forum's avatar
Altera_Forum
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15 years ago

VGA - horizantal sync pulse generation

hey, I am trying to generate horizantal sync pulse with FSM. I write the next verilog code: module horizantal_sync_pluse ( clock, //system clock reset, //system ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Another question.

I would like define

parameter Scan_Line=1'b0;

parameter Gen_Sync_Pulse=1'b1;

But I don't want that it will be showed in block diagram as parameter to change.

please see atachment.

How can I do it?

Thanks