Im new to this, coming from audio programming in MSP/Reaktor and lower level assembler. So I have to learn a lot about the FPGA stuff as I go along. But two things came to mind. It was hinted that higher and lower level coding and patching would not make as much of a difference as it does using these in computational languages. Is this so? Can I asume an all code project wether Verilog, VHDL or high level are more or less the same speed and size? And since im opting to learn one low level language which one should it be? For not running into trouble grabbing MIDI, buffers (RAM), waveform generation, HD's (sata), DAC's, ADC's and the likes..

From what Ive seen, High level languages (I assume you mean OpenCL or C-to-gates) can produce decent results in the hands of a skilled designer - but the same can be said of VHDL and Verilog. All three can produce very good and very bad results. So I cant says they will all produce the same results. The key is understanding the underlying architecture. If you dont understand the technology and try and write code as if you were a C programmer, you are doomed to fail in any language. As for which to chose - Verilog is more like C (C programmers seem to hate VHDL because of the strict rules) but it has some pitfalls because of this.

But they all the have the same end goal - so its just a question of which syntax you're most comfortable with. If you get fluent in one, then you should be able to read the other.

And Quartus has the high level visual logic blocks and pll's, right. Tho I think it's very cool to be able to use a lot of 1 bit signals and binary stuff. Mostly for the core modules I would be confortable using 24bit floating point numbers. and A=A+1 style counting. So it would be great to have that sort of thing in a readable format, but ofcourse there is nothing worse than finding out half way through things cant be done. I was looking at VHDL for the demo apps, it seems a bit double in it's expressions but slowly grasping it. So you say Verilog is worth checking out for audio, or am I going to hit a major wall somewhere?

--- Quote Start --- And Quartus has the high level visual logic blocks and pll's, right. Tho I think it's very cool to be able to use a lot of 1 bit signals and binary stuff. Mostly for the core modules I would be confortable using 24bit floating point numbers. and A=A+1 style counting. So it would be great to have that sort of thing in a readable format, but ofcourse there is nothing worse than finding out half way through things cant be done. I was looking at VHDL for the demo apps, it seems a bit double in it's expressions but slowly grasping it. So you say Verilog is worth checking out for audio, or am I going to hit a major wall somewhere? --- Quote End --- HDL design can be classified into 3 levels (usually mixed by users): structural: e.g. you instantiate a register directly wiring it, or instantiate an and function (ultimately mapped to luts) logic (or not exactly data flow): e.g. you a <= b and C behavioral: e.g. you describe in a sequential statement how a given node should behave. In all cases the compiler settles and maps the code to luts and registers and other prefabricated blocks like rams, multipliers...etc. It is certainly waste of time to go structural for things like registers which you can infer by behavioral description. You can also infer memories, multipliers (but not PLL) however I prefer structural approach to both rams and multipliers for good reasons as you may be given access to more features.

--- Quote Start --- I was looking at VHDL for the demo apps, it seems a bit double in it's expressions but slowly grasping it. So you say Verilog is worth checking out for audio, or am I going to hit a major wall somewhere? --- Quote End --- I may catch a lot of FLAK for this but I'd suggest you take a good look at VHDL first. It can do a few things Verilog can't like multi-dimensional arrays, nice functions and procedures.It has strict typing, which may look heavy in the beginning but you will get used to that after a while (and eventually end up liking that). There are a few VHDL editors that flag those syntax (and other) errors. E.g. Sigasi is a nice one, and for small projects it is free. There is also Emacs VHDL-mode. Verilog is often said to be more C-like, IMHO it isn't, but the 'inventors' put this down as a sales argument against VHDL, which effectively has it roots in the Pascal / Modula / Ada languages. Now I remember that C in the 80's allowed a lot of assignments without warnings, wreaking havoc at some point or later. In that view Verilog may be C-like ;) My boss at the time used to say: "If you get a Pascal program compiled, it will run to some point. If you C-source compiles, you are nowhere yet." There is also MyHDL, which is a Python based, it simulates fast and outputs either VHDL or Verilog for your Quartus project. Unfortunately it doesn't take advantage of VHDL's extra capabilities as it purposely supports both back-ends on an equal basis. There is also Cx and PSHDL, but those are not quite complete yet.

Verilog/VHDL versus high level functions. | Altera Community

22 Replies

Altera_Forum
Honored Contributor
11 years ago
Im in the process of drawing the core peice of FPGA on a peice of paper, and "paralelizing" parts of the design which used to be serial code.
But the thing i'm wondering about is based on the specs 50.000.000/192.000=~<260 logic operators per line is what im going to get "rigt?"
Is there a way to guestimate the timings? "bound to be shift operators and flipflofs" Or are there cycle charts maybe?
Altera_Forum
Honored Contributor
11 years ago
What kind of timings are you referring to? Latency can be calculated from how many register states you have. Clock speed is more down to what you have available and what throughput you need.

I'm not sure what you mean by number of logic operators? Is that how much logic there is between registers?
Altera_Forum
Honored Contributor
11 years ago
First off, I love VHDL from what I have seen it's exactly what I need it to be, I really love it. The strict part reminds me of assembler, while the formatting of controlled loops is exactly as I did it before. It's great :D The high frequency thing is awesome too alows me to mold the virtual analog sounding stuff.

So.. is the latency a matter of simply adding operators? (That would be when using the dsp?)
But it's hardware "right?" so is there the possibility for more logic operators in one clock, because the electrons travel through a steady state?
Altera_Forum
Honored Contributor
11 years ago
Latency is a matter of pipelining - which is a chain of registers, probably with some logic in between. Registers are inferred from VHDL from a basic template:

process(clk, areset) --remove areset if you dont want an async reset begin if areset = '1' then --remove if no reset needed --async reset elsif rising_edge(clk) then --do some stuff end if; end process;

So basically you count the number of signal assignments in the chain inside the clocked part of the process to calculate the latency. The less logic (ie gates) between registers and the faster you can run the clock. Remember that control logic (ifs/case etc) will get mapped to gates, so bare this in mind.

I highly recommended you stay away from any HDL until you have a good understanding of the basic logic elements. If you dont, and write some "bad" vhdl - it may simulate just fine but will either be terrible or just not compile at all for the FPGA.
Altera_Forum
Honored Contributor
11 years ago
So..about multiple processes in one peice of code. Do these become serial or paralel by default, or is there a way to tell the compiler this function goes under and this one after?

if areset = '1' then <--I see you do not close the sentence, nor use brackets.. musnt it be: if reset > '0' then A; --?
Oh I see its only at the paralel statements, but would it be bad practice to just and A?

Oh and one more the '1' brackets what do they mean?
Altera_Forum
Honored Contributor
11 years ago
All Processes are run in parrallel. You need to think in terms of hardware, not code. The clock will arrive at all processes at the same time, so all code is executed in parrallel.

No, you must check for if areset = '1'. This is a binary system - it will either be 1 or 0. Technically, if reset > '0' then will work, as '1' is defined after '0' in the std_logic definition. But it is not a good idea to use it.

single quotes '' are used to wrap around character types. std_logic is an enumerated type that uses characters for each state (it has 9 states in total, but only 3 are useful for real hardware ('1', '0' and 'Z'). The rest are just for simulation purposes : ('U', 'X', '-', 'H', 'L' and 'W')
Altera_Forum
Honored Contributor
11 years ago
Ah, so ideally one has to make a series of files discribing a "possibly tightly packed" paralel process.

I see in a binary scenario this would be useless to evaluate like that..

One more :D Is it possible to map functions directly to the output? Without describing the architecture..
Altera_Forum
Honored Contributor
11 years ago
I think you really really need to get a good book work work through a tutorial. It will explain things better than trying to ask here.

All entities need an architecture - an entity just describes the interface, and architecture describes the behaviour.
Altera_Forum
Honored Contributor
11 years ago
I mean if the interface node declares a variable that you are going to use in code, and the output does the same.
Wouldnt it be better practice even, to map these directly onto the output rather than creating an intermediate variable?
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
I mean if the interface node declares a variable that you are going to use in code, and the output does the same.
Wouldnt it be better practice even, to map these directly onto the output rather than creating an intermediate variable?
--- Quote End ---

What do you mean by interface node? do you mean a port? and variables are specific things in VHDL - they are different from signals.

Did you mean an intermediate signal?

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Verilog/VHDL versus high level functions.

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