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Altera_Forum
Honored Contributor
Honored ContributorVerilog/VHDL versus high level functions.
Im new to this, coming from audio programming in MSP/Reaktor and lower level assembler. So I have to learn a lot about the FPGA stuff as I go along. But two things came to mind. It was hint...
Altera_ForumHonored Contributor
Honored ContributorWhat kind of timings are you referring to? Latency can be calculated from how many register states you have. Clock speed is more down to what you have available and what throughput you need.
I'm not sure what you mean by number of logic operators? Is that how much logic there is between registers?
