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Altera_Forum's avatar
Altera_Forum
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11 years ago

Verilog/VHDL versus high level functions.

Im new to this, coming from audio programming in MSP/Reaktor and lower level assembler. So I have to learn a lot about the FPGA stuff as I go along. But two things came to mind. It was hint...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Im in the process of drawing the core peice of FPGA on a peice of paper, and "paralelizing" parts of the design which used to be serial code.

But the thing i'm wondering about is based on the specs 50.000.000/192.000=~<260 logic operators per line is what im going to get "rigt?"

Is there a way to guestimate the timings? "bound to be shift operators and flipflofs" Or are there cycle charts maybe?